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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4078B gates 8-input NOR gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 8-input NOR gate DESCRIPTION The HEF4078B provides the positive 8-input NOR function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. HEF4078B gates Fig.2 Pinning diagram. HEF4078BP(N): HEF4078BD(F): HEF4078BT(D): Fig.1 Functional diagram. 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category GATES See Family Specifications Fig.3 Logic diagram. January 1995 2 Philips Semiconductors Product specification 8-input NOR gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays In On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL 60 30 20 60 30 20 120 60 40 120 60 40 ns ns ns ns ns ns 10 15 tPLH tPHL 80 35 25 80 35 25 160 70 50 160 70 50 ns ns ns ns ns ns SYMBOL TYP. MAX. HEF4078B gates TYPICAL EXTRAPOLATION FORMULA 53 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 53 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 750 fi + (foCL) x VDD 2 2800 fi + (foCL) x VDD 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) 7500 fi + (foCL) x VDD 2 January 1995 3 |
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